1. Field of the Invention
The present invention relates to a high breakdown voltage semiconductor device.
2. Description of the Related Art
In a high breakdown voltage semiconductor device, dielectric isolation method is known an an effective method of isolating each element.
FIG. 1 shows a conventional high breakdown voltage diode obtained by using such a dielectric isolation method. Reference numeral 101 denotes a p.sup.+ type silicon substrate, and there is formed a substrate wafer in which the p.sup.+ type silicon substrate and an n.sup.- (or p.sup.-) type silicon substrate are bonded to each other by a direct bonding method. Reference numeral 102 is an oxide film of a bonding interface. The n.sup.- type substrate of the substrate wafer is selectively etched up to the depth reaching the oxide film 102, so that a groove is formed. Thereby, an n.sup.- type layer 103, which is an island element region, is formed. In the groove, an oxide film 104 is formed inside and a polycrystalline silicon film 105 is buried therein. An n.sup.+ type layer 106, serving as a cathode region, is formed in the central surface portion of the island n.sup.- type layer 103 isolated from other portions by the oxide films 102 and 104. Then, p.sup.+ type layer 107, serving as an anode region, is formed in the peripheral surface portion. As result, a diode is formed. P.sup.+ layers 108 and 109 are formed along the oxide films 102 and 104 so as to enclose the surroundings of the island n.sup.- type layer 103. The p.sup.+ type layers 108 and 109 are formed so as to allow large current to flow. A cathode electrode 110 and an anode electrode 111 are formed on the n.sup.+ type layer 106 and p.sup.+ type layer 107, respectively.
In the above diode, if reverse bias is applied to the portion between the anode and the cathode and a depletion layer extends to the n.sup.- type layer 103, and all applied voltages are applied between the n.sup.+ type layer 106 of the surface portion and the p.sup.+ type layer 108 of the bottom portion. Therefore, in order to obtain a diode having sufficient high breakdown voltage, it is required that a distance d between the n.sup.+ type layer 106 and the p.sup.+ type layer 108 be sufficiently largely made. More specifically, in order to obtain voltage of 600V, d=45 .mu.m is needed.
If the thickness of the n.sup.- type layer 103 is made larger so as to ensure the above-mentioned distance d, the groove for the element isolation in a lateral direction must be deepened in accordance with the thickness of the n.sup.- type layer 103. This makes it extremely difficult to perform the element isolation in the lateral direction.
As mentioned above, according to the semiconductor device having the conventional dielectric isolation structure, it is necessary to make the thickness of the high resistance semiconductor layer whose depletion layer extends sufficiently large so as to obtain a sufficient high breakdown voltage. Due to this, there is a problem that the element isolation becomes difficult to be performed.
The following explains the other examples of the semiconductor device having the conventional dielectric isolation structure.
FIG. 2 shows a conventional lateral type diode having the conventional dielectric isolation structure. An n.sup.- type silicon layer (active layer) 133 is formed on a semiconductor substrate 131 via an insulating film 132 for isolation. An n.sup.+ type layer 134 having a high impurity concentration is formed in the bottom portion of the active layer 133. A p-type anode layer 135 is formed in the active layer 133 and an n-type cathode layer 136 is formed in a portion which is away from the p-type anode layer 135 with a predetermined distance, and an anode electrode 137 and a cathode electrode 138 are formed on the anode layer 135 and the cathode layer 136, respectively.
In the above-mentioned lateral type diode, for example, considering a reverse bias state in which the anode electrode 137 and the substrate 131 are grounded and a positive voltage is applied to the cathode electrode 138, the voltage to be applied to the cathode is applied to the depletion layer extending to the active layer under the p-type anode layer 137, and the insulation film 132 for isolation.
Due to this, if the thickness of the active layer 133 under n-type cathode layer 136 is thin, a large electric field is shared at this portion, and an electric field concentration occurs in the vicinity of the curved portion of the bottom of the n-type cathode layer 136, and avalanche breakdown is generated at a low applied voltage. In order to avoid the above problem and realize the sufficient high breakdown voltage, the thickness of the active layer 133 is conventionally set to be 40 .mu.m or more.
However, if the thickness of the active layer is large, a deep isolation groove is needed for the element isolating in the lateral direction by a V-groove, and an area of the isolation groove reaction becomes large. Due to this, work processing becomes difficult and an effective area of the element becomes small, so that the cost of an integrated circuit having the high breakdown voltage element increases.
As mentioned above, in the high breakdown voltage semiconductor device having the conventional dielectric isolation structure, if the active layer is thin, a sufficient breakdown voltage cannot be obtained. Moreover, if the active layer is thick, the element isolation in the lateral direction becomes difficult.
On the other hand, there is known a conventional power IC in which a high breakdown voltage element such as a high breakdown voltage driving circuit and a low breakdown voltage device such as a low breakdown voltage control circuit are formed on a single substrate. There are various uses of this conventional power IC. For example, an inverter circuit may be produced by using p-channel FETs or IGBTs as high breakdown voltage devices, thereby simplifying a level shifter or a high-side gate circuit.
However, because of structural limitations of the device, the high breakdown voltage driving circuit and low breakdown voltage control circuit cannot be manufactured by a common process. Thus, one of them is first formed, and then the other. For example, in the prior art, when a p-channel high breakdown voltage MOSFET is fabricated, a deep p type well is formed, as in a DMOS, and the device is formed therein. Thus, there is no steps common to those of the process of forming a logic portion. Consequently, the number of steps, the time for manufacture and the manufacturing cost increase.
In addition, in the conventional high breakdown voltage MOSFET, the breakdown voltage decreases if the dosage of impurities in the active region is increased to reduce the turn-on resistance.